The present invention relates to a semiconductor device and to a method of manufacturing the same; and, more particularly, the invention relates to a technique that can effectively be applied to the manufacture of a semiconductor device, including a flattening process utilizing a CMP (Chemical Mechanical Polishing) method.
Trench isolation is one of the isolation methods employed for electrically isolating adjacent semiconductor elements. In a typical trench isolation fabrication process, grooves are provided on a semiconductor substrate which grooves become an element isolation region, and these grooves are filled with insulation films.
Trench isolation is formed, for example, using the following method. First, grooves are formed to a depth, for example, of about 0.4 xcexcm in the element isolation region of the semiconductor substrate using a dry etching method; and, thereafter, a first insulation film is formed to a thickness, for example, of about 20 nm at the surface where the semiconductor substrate is exposed by carrying out a thermal oxidation process on the semiconductor substrate. Thereafter, a second insulation film is deposited on the semiconductor substrate to fill the inside of the grooves; and, then, the trench isolation is formed by removing the portion of the second insulation film at the outside side of the grooves and leaving the portion of the second insulation film only inside of the grooves, through polishing of the surface of this second insulation film, for example, using the CMP method.
When the width of the element isolation region becomes relatively large, the polishing rate of the second insulation film becomes high in the local area during the CMP process, and, thereby, a so-called dishing phenomenon is easily generated, whereby a xe2x80x9crecessxe2x80x9d is produced at the central area of the grooves. However, several methods have been proposed to improve the flatness at the surface of the second insulation film in the element isolation region by controlling the dishing phenomenon. A method of providing a dummy pattern is one of such methods.
For example, the Japanese Patent Application Laid-Open No. Hei 10(1998)-92921, corresponding to the U.S. Pat. No. 5,885,856, discloses a method in which each dummy structure is placed in a non-active device area to cause the occupation density in the non-active device area to be equal to that of the active device area, and, thereby, the polishing rate is equalized for the entire part of the semiconductor substrate surface.
Moreover, the inventors of the present invention have considered a method of placing the dummy patterns in a regular manner. The technique explained below has been considered by the inventors of the present invention and its outline is as follows.
FIG. 28 shows a first dummy pattern placing method which the inventors of the present invention have considered.
A plurality of dummy patterns DPA, are regularly placed in a dummy region (region outside of the frame indicated by the broken line in the figure) FA, where semiconductor elements are not formed, outside of the element forming region (region within the frame of broken line in the figure) DA, where the semiconductor elements are formed. A plurality of dummy patterns DPA1 are formed to be equal in shape and size, and these dummy patterns are extensively placed with the same interval in the dummy region FA.
The element forming region DA and dummy region FA, outside of the active region AC, form element isolation region IS, and a trench isolation is usually formed in the entire part of this isolation region IS. Therefore, this method for regularly placing the dummy patterns has the inherent problem that the dishing phenomenon is easily generated during the CMP process, particularly in the dummy region FA, which is isolated from the active region AC. However, it is now possible to prevent such dishing phenomenon in the dummy region FA by placing a plurality of dummy patterns DP1 therein, whereby the flatness at the surface of the embedding insulation film in the dummy region FA can be improved.
FIG. 29 shows a second dummy pattern placing method which the inventors of the present invention have discussed. Like the method illustrated in FIG. 28, a plurality of dummy patterns DPA2 are regularly placed in the dummy region FA, where the semiconductor elements are not formed, outside of the element forming region DA, where the semiconductor elements are formed, and, thereby, the dishing in the dummy region FA can be prevented. The size of the dummy patterns DPA2 is smaller than the size of the dummy patterns DPA1 and the dummy patterns DPA2 can be placed up to the dummy region FA near the boundary BL (indicated by the frame line in the figure) between the element forming region DA and dummy region FA.
However, according to an investigation by the inventors of the present invention, there has been a further problem in that, when the dummy structures are placed in the non-active device area, some dummy structures are complicated in shape and the insulation film is not perfectly embedded within the internal side of the dummy structures which are particularly defined. Moreover, it has also been formed that the time required for the manufacturing process is extended because it is necessary to additionally provide a process for removing the dummy structures that are too small to be formed.
In addition, the inventors of the present invention have also found that the following problem exists in the first dummy pattern placing method and the second dummy pattern placing method.
In the first dummy pattern placing method, since the size of the dummy patterns DPA1 is relatively large, a region where the dummy patterns DPA1 cannot be placed is generated in the dummy region FA near the boundary BL between the element forming region DA and dummy region FA; and, if this region is extended relatively, it is apparent that the dishing phenomenon is generated.
In the second dummy pattern placing method, since the size of the dummy patterns DPA2 is relatively small, the dummy patterns DPA2 may be placed up to the area near the boundary BL between the element forming region DA and dummy region FA. Thereby, since the dummy patterns DPA2 may be placed also in the region where the dummy patterns DPA1 cannot be placed, the second dummy pattern placing method can further improve the flatness of the surface of the embedded insulation film up to the dummy region FA near the boundary BL in comparison with the first dummy pattern placing method.
However, when the second dummy pattern placing method is introduced, the number of dummy patterns DPA2 placed in the dummy region FA increases, and, thereby, the coordinate data required for generating a mask remarkably increases. As a result, there arises a problem in that the arithmetic processing time in computer used for generating a mask pattern increases, and, moreover, the time required for drawing the patterns on the mask substrate also increases, with the result that the throughput in the formation of a mask is remarkably deteriorated. Particularly, when the second dummy pattern placing method is employed for ASIC (Application Specific Integrated Circuit: integrated circuit for particular application), the time required to generate the mask is extended, with the result that a problem remains for development of ASIC within a short period of time.
It is therefore an object of the present invention to provide a technique to improve the flatness of the surface of members embedded in a plurality of recesses.
It is another object of the present invention to provide a technique to improve the flatness of the surface of members embedded in a plurality of recesses without extension of the time required for manufacturing the semiconductor device.
The objects explained above, other objects and novel features of the present invention will become more apparent from the following description of the present invention and the accompanying drawings.
The typical aspects of the invention disclosed in the present application will be briefly explained below.
(1) In the semiconductor device of the present invention, there are provided an element forming region where circuit elements are specified with the boundary and a dummy region where circuit elements adjacent to the boundary are not formed. The dummy region has at least two dummy pattern groups, each dummy pattern group allocates a plurality of dummy patterns in the same occupation shape on the plane and in the same size with isolation like a matrix, while maintaining also an equal interval between the patterns, and the sizes of a plurality of dummy patterns in the row direction and/or column direction are different among the dummy pattern groups.
(2) A method of manufacturing a semiconductor device of the present invention relates to a semiconductor device in which an element forming region where circuit elements are formed and a dummy region where circuit elements are not formed are specified with a boundary, and at least two dummy pattern groups are formed in the dummy region. The method comprises a process to form a first isolation groove for specifying an active region of the element forming region on the main surface of a semiconductor substrate and a second isolation groove for dividing, in a matrix shape, a plurality of dummy patterns forming a dummy pattern group in the dummy region; a process to deposit an insulation film covering the element forming region and dummy region so as to embed the first isolation groove and second isolation groove; and a process to remove the insulation film at the outside of the first isolation groove and second isolation groove by polishing the surface of insulation film, whereby a plurality of dummy patterns having the same occupation shape on the plane and the same size are formed in each dummy pattern group, but the sizes of dummy patterns in the row direction and/or column direction are different among the dummy pattern groups.
(3) A method of designing a semiconductor device of the present invention relates to a semiconductor device having an element forming region, where circuit elements are specified with a boundary, and a dummy region, where circuit elements are provided adjacent to the boundary. The dummy region has at least two dummy pattern groups, and a plurality of dummy patterns having the same occupation shape on the plane and the same size are disposed in a spaced arrangement like a matrix shape in each dummy pattern group and the sizes of a plurality of dummy patterns in the row direction and/or column direction are different among the dummy pattern groups. The method comprises a process to allocate, after specifying the element forming region and dummy region using the boundary, a plurality of dummy patterns for each dummy pattern group to generate a mesh of a size adding a size of one side of the dummy pattern forming the dummy pattern group and a size of the space among the adjacent dummy patterns for each dummy pattern group and allocate the dummy patterns within the mesh in the region where placement of dummy patterns is prohibited.
According to the features explained above, a plurality of dummy patterns can be placed up to the area near the boundary between the element forming region and dummy region. Thereby, the flatness of the surface of the insulation film embedded in the isolation grooves can be improved over the entire area of the dummy region.
Moreover, since a relatively wide region in the dummy region can be occupied by a plurality of dummy patterns of relatively wider area, while the remaining relatively narrow region can be occupied with a plurality of dummy patterns of relatively narrow area, an increase in the number of dummy patterns can be controlled. Therefore, an increase in the amount of coordinate data which needs to be produced at the time of generating a mask can also be controlled with a view toward controlling an increase in the arithmetic processing time of a computer used for such processing and the time for drawing a pattern on the mask substrate.